Although multi-Vt support is more difficult, designers looking for low-power performance are more likely to use body-bias techniques, which FD-SOI supports more readily than bulk silicon. The combination of forward and reverse body bias makes it possible to dynamically adjust switching performance and leakage.
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FinFET and UTB -SOI allows lower Vt and Vdd Lower power. • Body thickness is a new scaling parameter Better short channel effects to and beyond 10nm. • Undoped body Better mobility and random dopant fluctuation. • BSIM models of FinFET and UTBSOI are available – free Summary Chenming Hu, August 2011
Multi-VT Solution for FD-SOI withDual Metal Gate/Ground Plane Multi Vt requirement for SoC can be achieved for FDSOI device using dual WF metal-gate and ground-plane approach without back-bias 10/10/2017 SOITEC Confidential 23 FD-SOI technology-0,8-0,6-0,4-0,2 0 0,2 0,4 0,6 0,8 Threshold voltage (V)
• SOI-based devices differ from conventional silicon- built devices in that the silicon junction is above an electrical insulator, typically silicon dioxide or sapphire SOI Technology 7. • In a Silicon On Insulator (SOI) Fabrication technology , Transistors are encapsulated in SiO2 on all sides. SOI Technology 8.
– Can only be achieve by device geometry (FD-SOI) • Typical case: m≈1.3 – S = 1.3 * 26mV * ln10 ≈80 mV/dec @ RT – At worst case temperature (T=110C), S ≈100 mV/dec ox dep C C m dec mV q kT S ln10 ( ) ,= 1+ 18 V dd and V t Scaling ÖAs V t decreases, sub-threshold leakage increases ÖLeakage is a barrier to voltage scaling ...
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